Curriculum Vitae – LOU HUTTER

Employment History

Texas Instruments, Inc., Dallas, TX (TI)

  • 1978 – 1981 Process Engineer, DLIN-1 Wafer Fab
  • 1981 – 1990 Section Manager, DLIN-2 Wafer Fab
  • 1990 – 1995 Branch Manager, DLIN-2 Wafer Fab
  • 1995 – 2002 Department Manager, Process Development, Mixed-Signal Products Group
  • 2002 – 2007 Director, Mixed-Signal Technology Development, Silicon Technology Group

Dongbu HiTek, Seoul, S. Korea (DBH)

  • 2008 – 2012 Sr. Executive VP, GM of Analog Foundry Business Unit

Highlights of Qualifications

  • Extensive experience in process, component, and technology engineering and the management of leading-edge analog and mixed-signal technologies.
  • Senior VP and GM of an analog/power business unit at an Asian foundry responsible for technology, design kits, sales, marketing, and P&L.
  • Created an analog/power foundry business, growing revenues by a factor of 4 in 3 years by establishing leading-edge technology and relentlessly focusing on customers.
  • Was responsible for all mixed-signal technology development at TI, reporting to two Senior VPs for technology and products.
  • Expertise in high-power, high-precision, high-density, and high-speed CMOS and BiCMOS technologies down to 130nm sizes, power metallization and passives.
  • Ability to define a clear vision with leadership skills to motivate an organization.
  • Holder of 47 U.S. patents, and co-author of over 30 papers.
  • Elected a TI Fellow in 1995.

Selected Publications

  • “Gate oxide leakage and floating gate capacitor matching test,” ICMTS Proceedings, 2007
  • “Advanced analog processes provide essential system technology,” Semiconductor Network (Korea) and MicroElectronics (Taiwan), 2004
  •  “SiGe provides enabling technology for 3G wireless,” Wireless Design and Development, 2003
  • “The optimization of LBC6 power/mixed-signal IC BiCMOS process,” BCTM Proceedings, 2001
  •  “A highly manufacturable 0.25 μm RF technology utilizing a unique SiGe integration,” BCTM Proceedings, 2001
  • “Lead-Frame-On-Chip offers integrated power bus and bond over active circuit,” ISPSD Proceedings, 2001
  • “A performance comparison between new reduced surface drain ‘RSD’ LDMOS and RESURF and conventional planar power devices rated at 20V,” ISPSD Proceedings, 1997
  • “A 0.7um linear BiCMOS/DMOS technology for mixed-signal/power applications,” BCTM Proceedings, 1997
  • “A 30 V complementary bipolar technology on SOI for high speed precision analog circuits,” BCTM Proceedings, 1997
  • “16-60V rated LDMOS show advanced performance in a 0.72 um evolution BiCMOS power technology,” IEDM Proceedings, 1997
  • “Optimized 25V, 0.34 mΩ∙cm2 very-thin-RESURF (VTR), drain-extended IGFETs in a compressed BiCMOS process,” IEDM Proceedings, 1996
  • “A 1.0um linear BiCMOS technology with power DMOS capability,” BCTM Proceedings, 1995
  • “A 2.0 micron BiCMOS process including DMOS transistors for merged linear ASIC analog/digital/power applications,” APEC Proceedings, 1992
  • “BiCMOS technology for mixed-signal and power applications,” Analog & Mixed-Signal Design Conference Proceedings, 1992
  • “Solving the process integration challenges of BiCMOS,” Semiconductor International, 1989
  •  “BiCMOS processes for digital and analog devices,” Semiconductor International, 1989
  • "BiCMOS process technology", chapter in book entitled "BiCMOS technology and applications," edited by A.R. Alvarez, Kluwer Press, 1989 (2nd edition in 1993)

Selected Patents



  • 6,979,615 – System and method for forming a semiconductor with an analog capacitor using fewer structure steps
  • 6,737,326 – Method of integrating a thin-film resistor in a multi-level metal tungsten plug interconnect process
  • 6,706,635 – Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis
  • 6,683,380 – Integrated circuit with bonding layer over active circuitry
  • 6,396,109 – Isolated NMOS transistor fabricated in a digital BiCMOS process
  • 6,352,887 – Merged CMOS and bipolar circuit and method
  • 6,284,669 – Power transistor with silicide gate and contacts
  • 6,236,101 – Metallization outside protective overcoat for improved capacitors and inductors
  • 6,153,451 – Transistor with increased operating voltage and method of fabrication
  • 6,144,100 – Integrated circuit with bonding layer over active circuitry
  • 6,025,231 – Self-aligned DMOS transistor and method of fabrication
  • 5,825,065 – Low voltage DMOS transistor
  • 5,719,421 – DMOS transistor with low on-resistance and method of fabrication
  • 5,614,755 – High-voltage Schottky diode
  • 5,576,233 – Method for making an EEPROM with thermal oxide isolated floating gate
  • 5,489,547 – Method of fabricating a semiconductor device having polysilicon resistor with low temperature coefficient
  • 5,472,887 – Method for fabricating semiconductor device having high- and low-voltage MOS transistors
  • 5,436,179 – Semiconductor process for manufacturing semiconductor devices with increased operating voltages
  • 4,980,747 – Deep trench isolation with surface contact to isolation
  • 4,929,996 – Trench bipolar transistor
  • 4,994,887 – High voltage merged bipolar/CMOS technology
  • 4,805,071 – High voltage capacitor for integrated circuits
  • 5,576,233 – Method for making an EEPROM with thermal oxide isolated floating gate
  • 5,489,547 – Method of fabricating a semiconductor device having polysilicon resistorwith low temperature coefficient
  • 5,472,887 – Method for fabricating semiconductor device having high- and low-voltage MOS transistors
  • 5,436,179 – Semiconductor process for manufacturing semiconductor devices with increased operating voltages
  • 5,057,443 – Method for fabricating a trench bipolar transistor
  • 4,980,747 – Deep trench isolation with surface contact to isolation
  • 4,929,996 – Trench bipolar transistor
  • 4,994,887 – High voltage merged bipolar/CMOS technology
  • 4,805,071 – High voltage capacitor for integrated circuits